This invention relates to electrical inverters and more particularly to circuits for controlling power pole switching in pulse width modulated inverters.
Pulse width modulated DC-to-AC inverters approximate sine wave outputs by switching power pole switches at a rate higher than the fundamental sine wave frequency of the AC output. In the design of pulse width modulated DC-to-AC inverters, it is desirable to switch the power stage in a manner which reduces certain harmonics to low values so as to ease the burden of filtering the output power to obtain a sinusoidal voltage wave. Fairly small errors in switching times can produce harmonic voltages many times greater than desired. This usually results in the circuit filter being made considerably larger than theoretically necessary to suppress these harmonics.
In a transistor inverter, for example, it is necessary to provide an underlap condition to prevent shoot-through during the switching operation. This means that to switch an output point from one polarity to another, there must be a delay after the conducting transistor is turned off, to be sure it is no longer conducting, before the other transistor is turned on. Many times load conditions are such that the second transistor does not conduct at all since load current is shunted through a commutating diode, thereby shortening the switching time to that of the transistor turn-off time. The transistor switching time is quite variable depending on the instantaneous load current as well as the transistor turn-off characteristic. Therefore, the prescribed switching schedule may not be met, resulting in unpredicted harmonics.
The present invention minimizes output distortion due to switching errors by predicting the switching time required for each switching point and using this prediction to adjust the starting time for each switching period so that switching is accomplished on schedule. In general, a reference waveform which is to be reproduced at the power pole output will be available to the switching control circuitry. Pulses within the reference wave are to be reproduced at the power pole output after a preselected time interval. This delayed switching schedule is accomplished by measuring the power pole switching time for a plurality of inverter output pulses, averaging the measured switching times, and subtracting the average of these switching times from the preselected time interval to obtain a firing time period. The switching period for the corresponding pulse in the succeeding output cycle is then initiated at a point equal to the firing time period, as obtained from the average of the measured cycles, following a transition point in a reference waveform pulse. This process is repeated for each power pole output pulse. During steady state operation, it is reasonable to expect that switching periods will be the same length at corresponding switching points in each subsequent cycle. Therefore, the power pole will switch after a preselected time interval following the reference wave pulses.
A circuit which performs a similar delayed pole switching function, but without an averaging feature, is disclosed in my copending application, Ser. No. 355,073, filed Mar. 5, 1982 and entitled "Inverter Firing Control With Compensation for Variable Switching Delay", now U.S. Pat. No. 4,443,842. That application discloses a circuit and method for eliminating distortion in inverters caused by variability in switching delays of power poles, and is hereby incorporated by reference. Although tests of the circuit described in that application confirmed the operation as described, random instabilities occurred causing momentary disturbances in the output voltage of the inverter. An additional one of my copending applications, Ser. No. 490,261, filed concurrently with this application, and entitled "Inverter Firing Control With Error Compensation" also discloses a circuit which performs a delayed pole switching function without the averaging feature and is hereby incorporated by reference. This second application discloses a circuit which eliminates the need for a comparator circuit and ensures that only complete clock pulses are counted during the timing intervals.
A pole switch firing control circuit for controlling a pulse width modulated inverter constructed in accordance with this invention comprises: means for receiving a clock signal containing voltage pulses; means for generating a control signal having transition points for initiating a pole switch switching sequence in the inverter; a first counter, being presettable to start counting from a supplied number, for counting the number of clock voltage pulses which occur between a selected transition point in the control signal and the switching point of an associated pole switch and for dividing the counted number by a preselected number N to obtain an approximate average count equal to the sum of the supplied number and the counted number of clock pulses divided by N; means for storing the approximate average count counted by the first counter; means for generating the supplied number wherein the supplied number is equal to a selected previous approximate average multiplied by the factor (N-1)/N; and a second counter, being presettable to start counting at a selected previous approximate average count, and connected to count clock voltage pulses which occur after a preselected transition point in the reference signal until a preselected count has been reached, whereupon the second counter produces a carry output signal pulse which causes the means for generating a control signal to create a second transition point in the control signal to initiate a second pole switch switching sequence in the inverter. The sum of the number supplied to the first counter and the number of clock pulses which it counts divided by N, is equal to an approximate average of the number of clock pulses which have occurred during the preceding N switching cycles of the pole switch.
By appropriately timing the switching function, multiple phase inverters can be controlled by a single control circuit. The means for storing approximate average counts may be a shift register which stores the approximate average counts generated by the first counter during each switching sequence and delivers the appropriate stored approximate average count to the second presettable counter at an appropriate time to produce the desired inverter output wave form.
The circuit of this invention controls a switching of a power pole switch in a pulse width modulated inverter in accordance with a method comprising the steps of: measuring the switching time of a power pole switch for a polarity of switching cycles; averaging the measured switching delay time; subtracting the resulting average switching delay time from a preselected fixed time interval to obtain a firing time period; and initiating a switching sequence for the pole switch after a time equal to the firing time period following a transition point in a reference pulse signal.